tatooine is the library of reusable digital design modules for synthesis and simulation.
Synthesis-ready
| TOP NAME | HDL | COVERAGE STATUS | |||
|---|---|---|---|---|---|
| LINE | TOGGLE | COMB | FSM | ||
| AXIL2NATIVE | Verilog SystemVerilog | 98% | 60% | 72% | 100% |
| COMMON_CLOCK_FIFO | SystemVerilog | 0% | 0% | 0% | 0% |
| COUNTER | Verilog SystemVerilog | 100% | 15% | 64% | 100% |
| DDR_RING_BUFFER | SystemVerilog | 0% | 0% | 0% | 0% |
| DELTA_REG | Verilog SystemVerilog | 100% | 27% | 62% | 100% |
| EDGE_DETECTOR | Verilog SystemVerilog | 100% | 94% | 100% | 100% |
| FIXED_POINT_ABS | Verilog | 0% | 0% | 0% | 0% |
| FIXED_POINT_ACC | Verilog | 0% | 0% | 0% | 0% |
| FIXED_POINT_ADD | Verilog | 0% | 0% | 0% | 0% |
| FIXED_POINT_CHANGE_SIGN | Verilog | 0% | 0% | 0% | 0% |
| FIXED_POINT_COMP | Verilog | 0% | 0% | 0% | 0% |
| FIXED_POINT_MUL | Verilog | 0% | 0% | 0% | 0% |
| READ_ENGINE | Verilog | 100% | 27% | 84% | 100% |
| REGISTER_PIPELINE | SystemVerilog | 0% | 0% | 0% | 0% |
| RO_REG | Verilog SystemVerilog | 100% | 26% | 55% | 100% |
| RW_REG | Verilog SystemVerilog | 100% | 27% | 64% | 100% |
| SDPRAM | SystemVerilog | 0% | 0% | 0% | 0% |
| TDPRAM | SystemVerilog | 0% | 0% | 0% | 0% |
| random_gaussian | VHDL | 0% | 0% | 0% | 0% |
| random_uniform | VHDL | 0% | 0% | 0% | 0% |
Simulation-only
| TOP NAME | BRIEF DESCRIPTION | HDL |
|---|---|---|
| CLK_WIZARD | SystemVerilog |